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AS1710/AS1712
High-Output-Drive, 10MHz, 10V/s, Rail-to-Rail I/O O p A m ps w i t h S h u td o w n
D a ta S he e t
1 General Description
The AS1710/AS1712 are low-offset, high-output CMOS op amps that deliver 200mA of peak output current from a single supply (2.7 to 5.5V). These devices were specifically designed to drive typical headset levels (32), as well as bias RF power amplifiers for wireless handset applications. The devices are available as the standard products shown in Table 1. See also Ordering Information on page 16. Table 1. Standard Products Model AS1710A AS1710B AS1712A Description Single Op Amp with Shutdown Single Op Amp Quad Op Amp w/Shutdown Package SC70-6 SC70-5 TQFN-16 3x3mm
2 Key Features
! ! ! ! ! ! ! ! ! ! ! !
Constant Output Drive Capability: 50mA Rail-to-Rail Input and Output Supply Current: 1.6mA Single-Supply Operation: 2.7 to 5.5V Gain-Bandwidth Product: 10MHz High Slew Rate: 10V/s Voltage Gain: 100dB (RLOAD = 100k) Power-Supply Rejection Ratio: -85dB No Phase Reversal for Overdriven Inputs Unity-Gain Stable for Capacitive Loads: Up to 100pF Shutdown Mode (AS1710A) Current: 1nA typ Package Types: - SC70-6 - SC70-5 - TQFN-16 3x3mm
These rail-to-rail I/O, wide-bandwidth amplifiers exhibit a high slew rate of 10V/s and a gain-bandwidth product of 10MHz. The integrated shutdown feature (not included in B versions) drives the output low. These devices operate over the entire automotive temperature range (-40C to +125C).
3 Applications
The devices are ideal for portable/battery-powered audio applications, portable headphone speaker drivers (32), hands-free mobile phone kits, TFT panels, sound ports/cards, set-top boxes, biasing controls, DAC converter buffers, transformer/line drivers, motor drivers, and any other battery-operated audio device.
Figure 1. Typical Application
RF CIN RIN Headphone Jack to 32 Stereo Headset
Audio In Left
-
AS1710
COUT +
+
VBIAS
+
AS1710 Audio In Right CIN
COUT +
-
RIN RF
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AS1710/AS1712
Data Sheet - P i n o u t
4 Pinout
Pin Assignments
Figure 2. Pin Assignments (Top View)
IN+ 1
6 VDD
IN+ 1
5 VDD
VSS 2
AS1710-A SC70-6
5 SHDNN
VSS 2
AS1710-B SC70-5
4 OUT
IN- 3
4 OUT
IN- 3
14 OUT4
15 OUT1
16 IN1-
IN1+ 1 VDD 2 IN2+ 3 IN2- 4 OUT2 5 SHDNN1/2 6 SHDNN3/4 7 OUT3 8
13 IN412 IN4+ 11 VSS 10 IN3+ 9 IN3-
AS1712-A TQFN-16 3x3mm
Pin Descriptions
Table 2. Pin Descriptions Pin Number Pin Name IN+ INVDD VSS SHDNN OUT Description Non-inverting Input Inverting Input Positive Supply Input Negative Supply Input. This pin must be connected to ground in single-supply applications. Active Low Shutdown Control Amplifier Output
See Figure 2
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Data Sheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 3 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 4 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Absolute Maximum Ratings Parameter Supply Voltage (VDD to VSS) Supply Voltage (All Other Pins) Output Short-Circuit Duration to VDD or VSS Continuous Power Dissipation Thermal Resistance JA SC70-5 SC70-6 TQFN-16 3x3mm -40 -65 VSS - 0.3 Min Max +7 VDD + 0.3 1 247 245 33 +125 +150 +150 Units V V s mW C/W C C C The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC J-STD-020C "Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices". The lead finish for Pb-free leaded packages is matte tin (100% Sn). Derate at 31mW/C above 70C Derate at 31mW/C above 70C on PCB Comments
Operating Temperature Range Storage Temperature Range Junction Temperature
Package Body Temperature
+260
C
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AS1710/AS1712
Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
DC Electrical Characteristics
VDD = 2.7V, VSS = 0V, VCM = VDD/2, VOUT = VDD/2, RLOAD = Infinite, VSHDNN = VDD, TAMB = -40 to +125C. Typical values at TAMB = 25C. Table 4. DC Electrical Characteristics Symbol VDD VOFFSET IBIAS IOFFSET RIN VCM CMRR PSRR ROUT VOUT-SHDNN Parameter Supply Voltage Range Input Offset Voltage Input Bias Current Input Offset Current Input Resistance Common Mode Input Voltage Range Common Mode Rejection Ratio Power Supply Rejection Ratio Shutdown Output Impedance Shutdown Output Voltage Inferred from Common Mode 1 Rejection Ratio VSS < VCM < VDD VDD = 2.7 to 5.5V VSHDNN = 0V (A-Versions) VSHDNN = 0V, RLOAD = 2k to VDD (A-Versions) RLOAD = 100k AVOL Large Signal Voltage Gain VSS + 0.20V < VOUT < VDD - 0.20V RLOAD = 2k RLOAD = 200 RLOAD = 32 VOUT Output Voltage Swing VDD - VOH or VOL - VSS RLOAD = 200 RLOAD = 2k Output Voltage VDD - VOH or VOL - VSS ILOAD = 10mA, VDD = 2.7V ILOAD = 30mA, VDD = 5V 85 79 69 VSS -45 -70 -70 -85 130
1
Condition Inferred from Power Supply Rejection Ratio Test VCM = VSS to VDD VCM = VSS to VDD
Min 2.7 -3
Typ
Max 5.5
Unit V mV pA pA
0.6 50
1
1 1
+3
50
1000
M VDD V dB dB 300 mV
170 100 92 80 350 70 9 55 100 100
dB 650 120 20 100 mV 180 mV
IOUT
Output Source/Sink Current
VDD = 2.7V, V- = VCM, V+ = VCM100mV VDD = 5.0V, V- = VCM, V+ = VCM100mV VDD = 2.7V, VCM = VDD/2 VDD = 5.0V, VCM = VDD/2 VSHDNN = 0V VDD = 2.7V
mA 200 1.6 2.3 1 VSS + 0.3 VDD 0.3 50
1
IDD IDD-SHDNN
Quiescent Supply Current per OpAmp Output Shutdown Supply Current per OpAmp (A-Versions) SHDNN Logic Threshold (A-Versions) SHDNN Input Bias Current
3.2 4.6 2000
1
mA nA
Shutdown Mode Normal Operation VSS < VSHDNN < VDD (A-Versions)
V
pA
1. Guaranteed by design.
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Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s
AC Electrical Characteristics
VDD = 2.7V, VSS = 0V, VCM = VDD/2, VOUT = VDD/2, RLOAD = Infinite, VSHDNN = VDD, TAMB = -40 to +125C. Typical values at TAMB = 25C. Table 5. AC Electrical Characteristics Symbol GBWP FPBW SR PM GM THD+N CIN en Parameter Gain-Bandwidth Product Full-Power Bandwidth Slew Rate Phase Margin Gain Margin
1
Conditions VCM = VDD/2 VOUT = 2VP-P, VDD = 5V
Min
Typ 10 2.5 10 70 15
Max
Units MHz MHz V/s deg dB % pF
Total Harmonic Distortion Plus Noise Input Capacitance Voltage-Noise Density
1
f = 10kHz, VOUT = 2VP-P, AVCL = 1V/V
0.05 6
f = 1kHz f = 10kHz AVCL = 1V/V, no sustained oscillations
15 10 100 1 7 20
Hz
pF s s ns
nV/
Capacitive-Load Stability tSHDN tENABLE tON Shutdown Time (AS1710A) Enable Time from Shutdown (AS1710A) Power-Up Time
1. Guaranteed by design.
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Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
7 Typical Operating Characteristics
VDD = 2.7V; VSS = 0V, VCM = VDD/2, VOUT = VDD/2, RLOAD = , VSHDNN = VDD TAMB = +25C (unless otherwise specified). Figure 3. Gain and Phase vs. Frequency Figure 4. Gain and Phase vs. Frequency, CLOAD = 100pF
120
Gain
320 280 240
120
Gain
320 280 240
Phase
100 80
100 80
Gain (dB) .
Phase (deg)
Gain (dB) .
60 40 20 0 -20
Phase
200 160 120 80 40 0 100000
60 40 20 0 -20
200 160 120 80 40 0 100000
-40 0.001
0.1
10
1000
-40 0.001
0.1
10
1000
Frequency (kHz)
Frequency (kHz)
Figure 5. PSRR vs. Frequency
0 -10 -20
Figure 6. CMRR vs. Frequency
0 -10 -20
-40 -50 -60 -70 -80 -90
PSRR neg PSRR pos
CMRR (dB) .
PSRR (dB) .
-30
-30 -40 -50 -60 -70 -80 -90
CMRR
-100 0.001
0.1
10
1000
-100 0.001
0.1
10
1000
Frequency (kHz)
Frequency (kHz)
Figure 7. Supply Current vs. Temperature
4 3.5
Figure 8. Shutdown Current vs. Temperature
1000
.
Shutdown Current (nA)
.
Supply Current (mA)
3 2.5 2
2.7V 5V
100
10
1.5 1 0.5 0 -45
1
-20
5
30
55
80
105
130
0.1 -45
-20
5
30
55
80
105 130
Temperature (C)
Temperature (C)
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Phase (deg)
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Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
Figure 9. Supply Current vs. Common-Mode Voltage
3 2.5
5V
Figure 10. Input Voltage Noise vs. Frequency
1000
2 1.5
2.7V
Input Voltage Noise (nV/Hz)
3 4 5
Supply Current (mA)
.
.
100 1 0.5 0 0 1 2 10 1 0.001
0.1
10
1000
Common-Mode Voltage (V)
Frequency (kHz)
Figure 11. Output Voltage vs. Output Current, sourcing
5
5V
Figure 12. Output Voltage vs. Output Current, sinking
1.75
4.5
t<1s
1.5
Output Voltage (V) .
Output Voltage (V) .
4
t>10s
t>10s
3.5 3 2.5 2 1.5 1 0.5 0 50 100
t>10s t<1s 2.7V
1.25 1 0.75 0.5
2.7V t<1s
t>10s
t<1s
0.25 0 200 250 0 50
5V
150
100
150
200
Output Current (mA)
Output Current (mA)
Figure 13. Output Swing High vs. Temperature
100 90
Figure 14. Output Swing Low vs. Temperature
100 90
VOUT - VSS (mV) .
80
200
VOUT - VSS (mV) .
80
200
70 60 50 40 -45
70 60 50 40 -45
10mA
10mA
-20
5
30
55
80
105
130
-20
5
30
55
80
105
130
Temperature (C)
Temperature (C)
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Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
Figure 15. Transient Response, 100mV, 10pF load
Figure 16. Transient Response, 100mV, 100pF load
IN
50mV/DIV
IN
OUT
500ns/Div
OUT
500ns/Div
Figure 17. Transient Response, 1V, 10pF load
Figure 18. Transient Response, 1V, 100pF load
IN
500mV/DIV
IN
OUT
500ns/Div
OUT
500ns/Div
Figure 19. Transient Response, 2V, 10pF load
Figure 20. Transient Response, 2V, 100pF load
IN
1V/DIV
IN
OUT
500ns/Div
OUT
500ns/Div
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500mV/DIV
50mV/DIV
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AS1710/AS1712
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
8 Application Information
Package Power Dissipation
Caution: Due to the high output current drive, this op amp can exceed the absolute maximum power-dissipation rating. Normally, when peak current is less than or equal to 40mA the maximum package power dissipation is not exceeded for any of the package types offered. The absolute maximum power-dissipation rating of each package should always be verified. (EQ 1) gives an approximation of the package power dissipation: PPACKAGEDISS VRMS IRMS COS Where: VRMS is the RMS voltage from VDD to VOUT when sourcing current, and from VOUT to VSS when sinking current. IRMS is the RMS current flowing in or out of the op amp and the load. is the phase difference between the voltage and the current. For resistive loads, COS = 1. Figure 21. Typical AS1710/AS1712 Single-Supply Application
3.6V
(EQ 1)
R C VIN = 2VP-P R
+
AS1710
-
32
VRMS can be calculated as: VRMS (VDD - VDC) + VPEAK /2 Where: VDC is the DC component of the output voltage. VPEAK is the highest positive excursion of the AC component of the output voltage. For the circuit shown in Figure 21: VRMS = (3.6V - 1.8V) + 1.0V/2 = 2.507VRMS IRMS can be calculated as: IRMS IDC + (IPEAK/2) Where: IDC is the DC component of the output current. IPEAK is the highest positive excursion of the AC component of the output current. For the circuit shown in Figure 21: IRMS = (1.8V/32) + (1.0V/32)/2 = 78.4mARMS Therefore, for the circuit in Figure 21 the package power dissipation can be calculated as: PPACKAGEDISS = VRMS IRMS COS = 196mW Adding a coupling capacitor improves the package power dissipation because there is no DC current to the load, as shown in Figure 22 on page 10. (EQ 3) (EQ 2)
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AS1710/AS1712
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
60mW Single-Supply Stereo Headphone Driver
Two AS1710 amplifiers can be used as a single-supply, stereo headphone driver. The circuit shown in Figure 22 can deliver 60mW per channel with 1% distortion from a single 5V supply. Figure 22. Stereo Headphone Driver Application (with Coupling Capacitor)
RF RIN Headphone Jack to 32 Stereo Headset
Audio In Left
CIN
-
AS1710
COUT +
+
VBIAS
+
AS1710 Audio In Right
COUT +
-
CIN RIN RF
In Figure 22, CIN and RIN form a high-pass filter that removes the DC bias from the incoming signal. The -3dB point of the high-pass filter is given by: f-3dB = 1/(2RINCIN) (EQ 4)
Choose gain-setting resistors RIN and RF according to the amount of desired gain, keeping in mind the maximum output amplitude. COUT blocks the DC component of the amplifier output, preventing DC current flowing to the load. The output capacitor and the load impedance form a high-pass filter with the -3dB point determined by: f-3dB = 1/(2RLOADCOUT) For a 32 load, a 100F aluminum electrolytic capacitor gives a low-frequency pole at 50Hz. (EQ 5)
Rail-to-Rail Input Stage
The AS1710/AS1712 CMOS op amps have parallel connected N- and P-channel differential input stages that combine to accept a common-mode range extending to both supply rails. The N-channel stage is active for common-mode input voltages typically greater than (VSS + 1.2V), and the p-channel stage is active for common-mode input voltages typically less than (VDD - 1.2V).
Rail-to-Rail Output Stage
The minimum output is within millivolts of ground for single- supply operation, where the load is referenced to ground (VSS). Figure 23 shows the input voltage range and the output voltage swing of an AS1710 connected as a voltage follower. The maximum output voltage swing is load dependent although it is guaranteed to be within 500mV of the positive rail (VDD = 2.7V) even with maximum load (32 to ground).
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Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 23. Rail-to-Rail Input/Output Range, 100k
Figure 24. Rail-to-Rail Input/Output Range, 32
IN
1V/DIV
IN
OUT
VCC = 3.0V, RLOAD = 100k 2.5s/Div
OUT
VCC = 3.0V, RLOAD = 32 2.5s/Div
Note: The absolute maximum ratings (see page 3) for power dissipation and output short-circuit duration (10s, max) must be adhered to since the output current can exceed 200mA (see Typical Operating Characteristics on page 6).
Input Capacitance
The parallel-connected differential input stages for rail-to-rail operation results in relatively large input capacitance CIN (6pF typ). This introduces a pole at frequency (2RCIN)-1, where R is the parallel combination of the gain-setting resistors for the inverting or non-inverting amplifier configuration (Figure 25). If the pole frequency is less than or comparable to the unity-gain bandwidth (10MHz), the phase margin is reduced, and the amplifier exhibits degraded AC performance through either ringing in the step response or sustained oscillations. Figure 25. Inverting and Non-inverting Amplifiers with Feedback Compensation
Inverting CF RF AS1710 R VIN VOUT
R = R II RF RFCF = RCIN
VIN
Non-Inverting
+ -
-
AS1710 VOUT RF
+
CF R
The pole frequency is 10MHz when R = 2k. To maximize stability, R << 2k is recommended. To improve step response when R > 2k, connect a small capacitor (CF) between the inverting input and output. CF can be calculated by: CF = 6(R/RF) [pf] Where: RF is the feedback resistor. R is the gain-setting resistor. (EQ 6)
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AS1710/AS1712
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
Driving Capacitive Loads
The AS1710/AS1712 amplifiers have a high tolerance for capacitive loads, and are stable with capacitive loads up to 100pF. Figure 26 shows a typical non-inverting capacitive-load driving circuit in the unity-gain configuration. Figure 26. Capacitive-Load Driving Circuit
-
AS1710
RISO
+
CF
Note: Resistor RISO improves the circuit's phase margin by isolating the load capacitor from the AS1710/AS1712 output.
Power-Up
The AS1710/AS1712 typically settle within 5s after power-up.
Shutdown
When SHDNN (not included in B versions) is pulled low, supply current drops to 0.5A (per amplifier, VDD = 2.7V), the amplifiers are disabled, and their outputs are driven to VSS. Because the outputs are actively driven to VSS in shutdown, any pullup resistor on the output causes a current drain from the supply. Note: Pulling SHDNN high enables the amplifier. In the AS1712 the amplifiers shutdown in pairs. When exiting shutdown, there is a 6s delay before the amplifier output becomes active.
Power Supplies and Layout
The AS1710/AS1712 can operate from a single 2.7 to 5.5V supply or from dual 1.35 to 2.5V supplies. Good design improves device performance by decreasing the amount of stray capacitance at the op amp inputs/outputs.
! ! !
For single-supply operation, bypass the power supply with a 0.1F ceramic capacitor. For dual-supply operation, bypass each supply to ground. Decrease stray capacitance by placing external components close to the op amp pins, minimizing trace and lead lengths.
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AS1710/AS1712
Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
9 Package Drawings and Markings
Figure 27. SC70-5 Package
Notes: 1. 2. 3. 4. All dimensions are in millimeters. Dimensions are inclusive of plating. Dimensions are exclusive of mold flash and metal burr. All specifications comply with JEITA SC88A and JEDEC MO203.
Symbol e D b E HE Q1 A2 A1 A c L Lj
Min Max 0.65BSC 1.80 2.20 0.15 0.30 1.15 1.35 1.80 2.40 0.10 0.40 0.80 1.00 0.00 0.10 0.80 1.10 0.10 0.18 0.10 0.30 0.26 0.46
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AS1710/AS1712
Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
Figure 28. SC70-6 Package
Notes: 1. 2. 3. 4. All dimensions are in millimeters. Dimensions are inclusive of plating. Dimensions are exclusive of mold flash and metal burr. All specifications comply with JEITA SC88 and JEDEC MO203.
Symbol e D b E HE Q1 A2 A1 A c L Lj
Min Max 0.65BSC 1.80 2.20 0.15 0.30 1.15 1.35 1.80 2.40 0.10 0.40 0.80 1.00 0.00 0.10 0.80 1.10 0.10 0.18 0.10 0.30 0.26 0.46
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Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
Figure 29. TQFN-16 3x3mm Package
-A-
D
INDEX AREA (D/2 xE/2) 4
D2 D2/2
-B-
D/2
E/2
NXL
e
E2/2
aaa C 2x
-BSEE DETAIL B 2 1
6 SEE DETAIL B
-A-
aaa C 2x TOP VIEW
N N-1
INDEX AREA (D/2 xE/2)
NXb bbb ddd
5 CA B C
Datum A or B
4
BTM VIEW
L1
ccc C NX 0.08 C
A
A1
Terminal Tip ODD TERMINAL SIDE 5
Symbol aaa bbb ccc ddd b A A1 A3 e Notes: 1. 2. 3. 4.
Min
0.18 0.70 0.00
Typ 0.15 0.10 0.10 0.05 0.25 0.75 0.02 0.20REF
Max
0.30 0.80 0.05 0.50
Notes 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2
Symbol L1 D BSC E BSC D2 E2 L N ND NE
Min 0.03
Typ 3.00 3.00 1.45 1.45 0.40 16 4 4
Max 0.15
1.30 1.30 0.30
1.55 1.55 0.50
5.
6. 7.
8.
Dimensioning and tolerancing conform to ASME Y14.5m-1994. All dimensions are in millimeters while angle is in degrees (). N is the total number of terminals. The terminal #1 identifier and terminal numbering convention shall conform to JEDEC 95, SPP-002. Details of terminal #1 identifier are optional, but must be located within the zone indicated. The terminal #1 identifier may be either a mold or marked feature. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension b should not be measured in that radius area. Depopulation is possible in a symmetrical fashion. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension b should not be measured in that radius area. ND and NE refer to the number of terminals on sides D and E respectively.
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A3
e
SIDE VIEW
SEATING PLANE -C-
Notes 1, 2 1, 2, 8 1, 2, 8 1, 2, 8 1, 2, 8 1, 2, 8 1, 2, 8 1, 2, 8
E2
E
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AS1710/AS1712
Data Sheet
10 Ordering Information
The device is available as the standard products shown in Table 6. Table 6. Ordering Information Model AS1710A-ASCT AS1710B-ASCT AS1712A-AQFT Description Single Op Amp with Shutdown Single Op Amp Quad Op Amp with Shutdown Delivery Form Tape and Reel Tape and Reel Tape and Reel Package SC70-6 SC70-5 TQFN-16 3x3mm
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AS1710/AS1712
Data Sheet - O r d e r i n g I n f o r m a t i o n
Copyrights
Copyright (c) 1997-2007, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered (R). All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters austriamicrosystems AG A-8141 Schloss Premstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact
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